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| the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. mos integrated circuit pd444008l 4m-bit cmos fast sram 512k-word by 8-bit data sheet document no. m14429ej6v0ds00 (6th edition) date published september 2006 ns cp(k) printed in japan the mark 2 pd444008l data sheet m14429ej6v0ds pin configuration (marking side) / indicates active low signal. 36-pin plastic soj (10.16 mm (400)) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 a0 a1 a2 a3 a4 /cs i/o1 i/o2 v cc gnd i/o3 i/o4 /we a5 a6 a7 a8 a9 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 nc a18 a17 a16 a15 /oe i/o8 i/o7 gnd v cc i/o6 i/o5 a14 a13 a12 a11 a10 nc a0 - a18 : address inputs i/o1 - i/o8 : data inputs / outputs /cs : chip select /we : write enable /oe : output enable v cc : power supply gnd : ground nc : no connection remark refer to package drawing for the 1-pin index mark. 3 pd444008l data sheet m14429ej6v0ds block diagram a0 | a18 address buffer row decoder memory cell array 4,194,304 bits gnd v cc /we /oe /cs input data controller sense amplifier / switching circuit column decoder address buffer i/o1 | i/o8 output data controller truth table /cs /oe /we mode i/o supply current h not selected high impedance i sb l l h read d out i cc l l write d in l h h output disable high impedance remark : don?t care 4 pd444008l data sheet m14429ej6v0ds electrical specifications absolute maximum ratings parameter symbol condition rating unit supply voltage v cc ?0.5 note to +4.0 v input / output voltage v t ?0.5 note to +4.0 v operating ambient temperature t a 0 to 70 c storage temperature t stg ?55 to +125 c note ?2.0 v (min.) (pulse width : 2 ns) caution exposing the device to stress above those listed in absolute maximum rating could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this speci fication. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol condition min. typ. max. unit supply voltage v cc 3.0 3.3 3.6 v high level input voltage v ih 2.0 v cc +0.3 v low level input voltage v il ?0.3 note +0.8 v operating ambient temperature t a 0 70 c note ?2.0 v (min.) (pulse width : 2 ns) 5 pd444008l data sheet m14429ej6v0ds dc characteristics (recommended operating conditions unless otherwise noted) parameter symbol test condition min. typ. max. unit input leakage current i li v in = 0 v to v cc ?2 +2 a output leakage current i lo v i/o = 0 v to v cc , ?2 +2 a /cs = v ih or /oe = v ih or /we = v il operating supply current i cc /cs = v il , cycle time : 8 ns 185 ma i i/o = 0 ma, cycle time : 10 ns 165 minimum cycle time cycle time : 12 ns 155 standby supply current i sb /cs = v ih , v in = v ih or v il 40 ma i sb1 /cs v cc ? 0.2 v, 5 v in 0.2 v or v in v cc ? 0.2 v high level output voltage v oh i oh = ?4.0 ma 2.4 v low level output voltage v ol i ol = +8.0 ma 0.4 v remark v in : input voltage v i/o : input / output voltage capacitance (t a = 25 c, f = 1 mhz) parameter symbol test condition min. typ. max. unit input capacitance c in v in = 0 v 6 pf input / output capacitance c i/o v i/o = 0 v 8 pf remarks 1. v in : input voltage v i/o : input / output voltage 2. these parameters are periodica lly sampled and not 100% tested. 6 pd444008l data sheet m14429ej6v0ds ac characteristics (recommended operati ng conditions unless otherwise noted) ac test conditions input waveform (rise and fall time 3 ns) test points gnd 3.0 v 1.5 v 1.5 v output waveform test points 1.5 v 1.5 v output load ac characteristics directed with the note s hould be measured with t he output load shown in figure 1 or figure 2 . figure 1 figure 2 (t aa , t acs , t oe , t oh ) (t clz , t olz , t chz , t ohz , t whz , t ow ) v tt = +1.5 v i/o (output) 50 z o = 50 30 pf c l +3.3 v i/o (output) 317 5 pf c l 351 remark c l includes capacitances of the probe and jig, and stray capacitances. 7 pd444008l data sheet m14429ej6v0ds read cycle parameter symbol -a8 -a10 -a12 unit notes min. max. min. max. min. max. read cycle time t rc 8 10 12 ns address access time t aa 8 10 12 ns 1 /cs access time t acs 8 10 12 ns /oe access time t oe 4 5 6 ns output hold from address change t oh 3 3 3 ns /cs to output in low impedance t clz 3 3 3 ns 2, 3 /oe to output in low impedance t olz 0 0 0 ns /cs to output in high impedance t chz 4 5 6 ns /oe to output hold in high impedance t ohz 4 5 6 ns notes 1. see the output load shown in figure 1 . 2. transition is measured at 200 mv from steady-state voltage with the output load shown in figure 2 . 3. these parameters are periodica lly sampled and not 100% tested. read cycle timing chart 1 (address access) t oh t rc t aa address (input) i/o (output) previous data out data out remarks 1. in read cycle, /we should be fixed to high level. 2. /cs = /oe = v il 8 pd444008l data sheet m14429ej6v0ds read cycle timing chart 2 (/cs access) address (input) t rc t aa t olz /cs (input) i/o (output) data out t ohz high impedance t acs /oe (input) t oe t clz t chz high impedance caution address valid prior to or co incident with /cs low level input. remark in read cycle, /we should be fixed to high level. 9 pd444008l data sheet m14429ej6v0ds write cycle parameter symbol -a8 -a10 -a12 unit notes min. max. min. max. min. max. write cycle time t wc 8 10 12 ns /cs to end of write t cw 6 7 8 ns address valid to end of write t aw 6 7 8 ns write pulse width t wp 6 7 8 ns data valid to end of write t dw 4 5 6 ns data hold time t dh 0 0 0 ns address setup time t as 0 0 0 ns write recovery time t wr 0 0 0 ns /we to output in high impedance t whz 4 5 6 ns 1, 2 output active from end of write t ow 3 3 3 ns notes 1. transition is measured at 200 mv from steady-state voltage with the output load shown in figure 2 . 2. these parameters are periodica lly sampled and not 100% tested. write cycle timing chart 1 (/we controlled) t wc t cw t wp t as t wr address (input) /cs (input) /we (input) i/o (input / output) t dh t whz t aw high impe- dance high impe- dance t ow indefinite data out data in indefinite data out t dw cautions 1. /cs or /we should be fixed to high level during address transition. 2. do not input data to the i/o pins while they are in the output state. remarks 1. write operation is done during t he overlap time of a low level /cs and a low level /we. 2. when /we is at low level, the i/o pins are always high impedance. when /we is at high level, read operation is executed. t herefore /oe should be at high level to make the i/o pins high impedance. 10 pd444008l data sheet m14429ej6v0ds write cycle timing chart 2 (/cs controlled) t wc t as t cw t aw t wp t wr t dw t dh address (input) /cs (input) /we (input) i/o (input) high impedance data in high impedance cautions 1. /cs or /we should be fixed to high level during address transition. 2. do not input data to the i/o pins while they are in the output state. remark write operation is done during the overlap time of a low level /cs and a low level /we. 11 pd444008l data sheet m14429ej6v0ds package drawing m n k m q g h j e t u b c d e f g h i j k 23.6 0.20 11.18 0.2 1.005 0.1 0.74 3.5 0.2 2.545 0.2 0.8 min. 10.16 0.1 note p q 0.1 9.4 0.20 0.12 0.42 1.27 (t.p.) 2.6 each lead centerline is located within 0.12 mm of its true position (t.p.) at maximum material condition. m n t u 0.22 r 0.85 + 0.08 ? 0.07 36-pin plastic soj (10.16 mm (400)) p36le-400a-2 item millimeters + 0.08 ? 0.07 19 18 36 1 s s i f p c d b 12 pd444008l data sheet m14429ej6v0ds recommended soldering conditions please consult with our sales offi ces for soldering conditions of the pd444008l. type of surface mount device pd444008lle : 36-pin plastic soj (10.16 mm (400)) pd444008lle-a : 36-pin plastic soj (10.16 mm (400)) quality grade ? a quality grade of the products is ?standard?. ? anti-radioactive design is not implemented in the products. ? semiconductor devices have the possibilit y of unexpected defects by affection of cosmic ray that reach to the ground and so forth. 13 pd444008l data sheet m14429ej6v0ds revision history edition/ page type of location description date this previous revision (previous edition this edition) edition edition 6th edition/ p.12 p.12 addition quality grade section of quality grade has been added. sep. 2006 14 pd444008l data sheet m14429ej6v0ds [ memo ] 15 pd444008l data sheet m14429ej6v0ds 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6 pd444008l the information in this document is current as of september, 2006. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) (1) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. (2) "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). ? ? ? ? ? ? m8e 02. 11-1 |
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